The present disclosure relates to solid-state imaging elements, driving methods, and electronic apparatus, and particularly to a solid-state imaging element, a driving method, and electronic apparatus that allow enhancement in the image quality of taken images.
In an image sensor to read out a charge accumulated by a light receiving part via a MOS (Metal Oxide Semiconductor) transistor, it is preferable that the charge be so transferred to a charge-voltage conversion part (so-called floating diffusion, hereinafter referred to also as FD) that the light receiving part becomes fully-depleted in order to read out all of the accumulated charge.
However, if a supply voltage is lowered for the purpose of power saving for example, the voltage of the FD when the FD is reset (reset voltage) decreases corresponding to the lowering of the supply voltage and therefore it becomes difficult to set the light receiving part to the fully-depleted state and completely transfer the accumulated charge. To completely transfer the accumulated charge even when the reset voltage of the FD is lowered, the light receiving part needs to be so designed as to have a shallow potential. However, this reduces the amount of saturation charge.
So, a related-art technique to address this problem has been disclosed. In this technique, a higher voltage is applied by a power supply line or a vertical signal line of the pixel in transfer of the accumulated charge in the light receiving part after the FD is reset to a predetermined voltage. Thereby, the voltage of the FD in a floating state is set high by coupling of parasitic capacitance between the power supply line or the vertical signal line of the pixel and the FD, and the accumulated charge in the light receiving part is easily completely transferred (refer to e.g. Japanese Patent Laid-open No. 2005-86225 and Japanese Patent Laid-open No. 2005-192191).
Another related-art technique has also been disclosed. In this technique, after the FD is reset to a predetermined voltage, a selection signal input to a selection transistor is turned to the active state (turned to a high level). Thereby, the voltage of the FD in the floating state is set high by coupling of parasitic capacitance between the selection signal line to input the selection signal and the FD, and the accumulated charge in the light receiving part is easily completely transferred (refer to e.g. Japanese Patent Laid-open No. 2009-26892 and Japanese Patent Laid-open No. 2009-130679).
As just described, there have been proposed techniques in which a high voltage is applied by an existing signal line such as the power supply line or the vertical signal line of the pixel or the selection signal line to thereby set the voltage of the FD high and easily completely transfer the accumulated charge in the light receiving part.